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Clocking Analysis, Implementation and Measurement Techniques for High-Speed Data Links-A Tutorial
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DOI：10.1109/TCSI.2008.931647.png)
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摘要
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The performance of high-speed wireline data links depend crucially on the quality and precision of their clocking infrastructure. For future applications, such as microprocessor systems that require terabytes/s of aggregate bandwidth, signaling system designers will have to become even more aware of detailed clock design tradeoffs in order to jointly optimize I/O power, bandwidth, reliability, silicon area and testability. The goal of this tutorial is to assist I/O circuit and system designers in developing intuitive and practical understanding of I/O clocking tradeoffs at all levels of the link hierarchy from the circuit-level implementation to system-level architecture.
Keyword:
Clock distribution
clock recovery
high-speed I/O
phase-locked loops
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