.png){kind=icon}
返回
Custom Instructions for Networked Processor Templates
.png){kind=icon}
PRE
AI
DOI：10.1109/TCSII.2022.3178389.png)
.png){kind=icon}
原文求助.png){kind=icon}
分享.png){kind=icon}
收藏
摘要
En 中文
As Field-programmable Gate Arrays (FPGAs) continue to increase in size and capability, there is an increasing need to develop performant designs in good time. Networked processor templates support scalable on-chip parallelism while avoiding the complexity and long run time of FPGA synthesis tools. The performance of the resulting designs can be further enhanced by adding custom instructions to processors in the network. We show how to systematically choose parts of a design to implement as custom instructions. We illustrate the use of performance and area models targeting a particular networked processor template to explore design trade-offs. Various applications, such as N-body simulation and dissipative particle dynamics, demonstrate how hardware acceleration based on custom instructions can target state-of-the-art FPGAs.
Keyword:
Solid modeling
Field programmable gate arrays
Adaptation models
Computational modeling
Tutorials
Throughput
Predictive models
Field programmable gate arrays
high level synthesis
期刊
I
IF:
4.9
论文数:
8.8K
被引数:
2.5W
机构
引用论文
.png){kind=icon}
Thermodynamic and experimental study of diamond deposition from a CH4H2 gas mixtureCH4H2气体混合物中金刚石沉积的热力学与实验研究
PREAI
分享收藏Towards extreme scale dissipative particle dynamics simulations using multiple GPGPUs使用多个gpgpu进行极端尺度耗散粒子动力学模拟
OAAI
OAAI分享收藏Imaging and characterization of film coating using scanning acoustic microscopy使用扫描声学显微镜对薄膜涂层进行成像与表征
PREAI
分享收藏
查看更多内容