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Customizable Computing-From Single Chip to Datacenters

delete2019-01-01
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OA
AI
J
Jason Cong *
Z
Zhenman Fang
M
Muhuan Huang
P
Peng Wei
D
Di Wu
C
Cody Hao Yu
DOI:10.1109/JPROC.2018.2876372delete
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摘要

摘要

En 中文
Since its establishment in 2009, the Center for Domain-Specific Computing (CDSC) has focused on customizable computing. We believe that future computing systems will be customizable with extensive use of accelerators, as custom-designed accelerators often provide 10-100X performance/energy efficiency over the general-purpose processors. Such an accelerator-rich architecture presents a fundamental departure from the classical von Neumann architecture, which emphasizes efficient sharing of the executions of different instructions on a common pipeline, providing an elegant solution when the computing resource is scarce. In contrast, the accelerator-rich architecture features heterogeneity and customization for energy efficiency; this is better suited for energy-constrained designs where the silicon resource is abundant and spatial computing is favored-which has been the case with the end of Dennard scaling. Currently, customizable computing has garnered great interest; for example, this is evident by Intel's $17 billion acquisition of Altera in 2015 and Amazon's introduction of field-programmable gate-arrays (FPGAs) in its AWS public cloud. In this paper, we present an overview of the research programs and accomplishments of CDSC on customizable computing, from single chip to server node and to datacenters, with extensive use of composable accelerators and FPGAs. We highlight our successes in several application domains, such as medical imaging, machine learning, and computational genomics. In addition to architecture innovations, an equally important research dimension enables automation for customized computing. This includes automated compilation for combining source-code-level transformation for high-level synthesis with efficient parameterized architecture template generations, and efficient runtime support for scheduling and transparent resource management for integration of FPGAs for datacenter-scale acceleration with support to the existing programming interfaces, such as MapReduce, Hadoop, and Spark, for large-scale distributed computation. We will present the latest progress in these areas, and also discuss the challenges and opportunities ahead.
Keyword:
Accelerator-rich architecture
CPU-FPGA
customizable computing
FPGA cloud
specialized acceleration
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Proceedings of the IEEE 封面图
Proceedings of the IEEE
IF:
25.9
论文数:
9.9K
被引数:
4.5W

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University of California System 封面图
University of California System
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论文数: 33.8W
被引数: 6.6K
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