Data-flow analysis and optimization for data coherence in heterogeneous architectures

Rafael T. de Sousa

doi:10.1016/j.jpdc.2019.04.004

Data-flow analysis and optimization for data coherence in heterogeneous architectures

2019-08-01

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Fernando Magno Quintão Pereira

G

Guido Araújo

DOI：10.1016/j.jpdc.2019.04.004

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Although heterogeneous computing has enabled developers to achieve impressive program speed-ups, the cost of moving and keeping data coherent between host and device may easily eliminate any performance gains achieved by acceleration. To deal with this problem, this paper introduces DCA: a pair of two data-flow analyses that determine how variables are used by host/device at each program point. It also introduces DCO, a code optimization technique that uses DCA information to: (a) allocate OpenCL shared buffers between host and devices; and (b) insert appropriate OpenCL function calls into program points so as to minimize the number of data coherence operations. We have used the AClang compiler to measure the impact of DCA and DCO when generating code from Parboil, Polybench and Rodinia benchmarks for a set of discrete/integrated CPUs. The experimental results showed speed-ups of up to 5.25x (average of 1.39x) on an ARM Mali-T880 and up to 8.87x (average of 1.66x) on an NVIDIA GPU Pascal Titan X. (C) 2019 Elsevier Inc. All rights reserved.

Keyword:

Compilers

Data coherence

Heterogeneous architectures

Data-flow analysis and optimization for data coherence in heterogeneous architectures

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