Debugging Circuit for Detecting Timing Errors in Serializer for High-Speed Wireline Interfaces

Jong‐Chan Lee

doi:10.1109/ACCESS.2024.3492235

2024-01-01

Jong‐Chan Lee

Joo‐Hyung Chae *

DOI：10.1109/ACCESS.2024.3492235

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摘要

En 中文

Several circuit components can induce bit errors at high-speed wireline interfaces. Hence, accurate identification and correction of error points in various circuits using straightforward techniques are crucial. A serializer in the transmitter may experience abnormal operations due to a timing mismatch between data and clock signals, leading to bit errors. Hence, we propose a debugging circuit to address this challenge for detecting timing mismatches between input data and clock signals within the tri-state inverter-based 2:1 serializer with a half-rate clocking architecture. The debugging circuit uses a true single-phase clocked (TSPC) DFF, TSPC latch, and XOR gate, which are simple complementary metal-oxide-semiconductor (CMOS) logics, and did not necessitate additional pads or experimental equipment, resulting in minimal area occupation and low power consumption. Using identical data and clock signals with the 2:1 serializer, the timing relationship between the data and clock signals can be detected. Unlike complex debugging methods that rely on intricate algorithms and extensive programming, our approach simplifies debugging, reducing test time. We developed a prototype transmitter using a 28-nm CMOS process to validate the effectiveness of our proposed solution. The 2:1 serializer was designed to function correctly or not by manually adjusting the input clock phase for testability. The proposed debugging circuit effectively detected timing mismatches in the serializer at speeds up to 7.5 Gb/s. The circuit occupied only 0.4% of the total area and consumed only 0.2% of the total transmitter power.

Keyword:

Timing

Debugging

Clocks

Latches

Logic gates

Transmitters

Synchronization

Power demand

Noise measurement

Logic

half-rate clock