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Decoder Design for RS-Based LDPC Codes
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DOI：10.1109/TCSII.2009.2027945.png)
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This brief studies very large-scale integration (VLSI) decoder architectures for RS-based low-density parity-check (LDPC) codes, which are a special class of LDPC codes based on Reed-Solomon codes. The considered code ensemble is well known for its excellent error-correcting performance and has been selected as the forward error correction coding scheme for 10GBase-T systems. By exploiting the shift-structured properties hidden in the algebraically generated parity-check matrices, novel decoder architectures are developed with significant advantages of high level of parallel decoding, efficient usage of memory, and low complexity of interconnection. To demonstrate the effectiveness of the proposed techniques, we completed a high-speed decoder design for a (2048, 1723) regular RS-LDPC code, which achieves 10-Gb/s throughput with only 820 000 gates. Furthermore, to support all possible RS-LDPC codes, two special cases in code construction are considered, and the corresponding extensions of the decoder architecture are investigated.
Keyword:
Error correction codes
low-density parity-check (LDPC) codes
parallel processing
very large-scale integration
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4.9
论文数:
8.8K
被引数:
2.5W
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