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Decomposition Approaches for Power Reduction
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DOI：10.1109/ACCESS.2023.3260970.png)
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The article discusses a synthesis strategy aimed at reducing power consumption consumed by logic structures implemented in FPGAs. The essence of the method is to carry out multioutput function decomposition, which takes into account the problem of dynamic power reduction. The article presents several techniques leading to such a reduction: preliminary ordering of variables taking into account the probabilities of occurrence of the value 1 for individual variables, reduction of the number of LUTs by limiting the number of bound functions, and in particular bicoding or appropriate unicoding taking into account the need to reduce power for the implementation of multioutput functions. These techniques have been combined into a coherent synthesis strategy called PowerdekBDD, which is an extension of the DekBDD strategy, which is the result of many years of work in the area of logic synthesis using BDD graphs. The article contains the results of experiments confirming the effectiveness of the presented strategy.
Keyword:
Power demand
Logic gates
Field programmable gate arrays
Switches
Table lookup
Heuristic algorithms
Digital systems
Decomposition
FPGA
low power synthesis
switching activity
technology mapping
期刊
IF:
3.6
论文数:
9.8W
被引数:
29.4W
机构
引用论文
Methods of Improving Time Efficiency of Decomposition Dedicated at FPGA Structures and Using BDD in the Process of Cyber-Physical Synthesis.png)
IEEE ACCESS
OAAI
IEEE ACCESSIF3.6
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