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Design and analysis of hybrid complementary metal-oxide-semiconductor gate diffusion input technology based power efficient converter
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DOI：10.1016/j.compeleceng.2026.111320.png)
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Abstract
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The growing need for energy-efficient and high-resolution data converters in medical and embedded systems dictates the need to have architectures that strike the right balance between power consumption, robustness, and conversion accuracy. Hybrid logic approaches, including pass-transistor logic and Gate Diffusion Input (GDI) techniques, have been investigated in Successive Approximation Register Analog-to-Digital Conversion SAR-ADC designs. Existing architectures lack a systematic methodology for the distribution of critical and non-critical logic blocks. This research presents a 16-bit time-sensitive HCMOS-GDI (Hybrid Complementary Metal-Oxide-Semiconductor and Gate Diffusion Input) based SAR-ADC designed using 250 nm technology, integrating CMOS and GDI logic to achieve lower power consumption and higher operating speed. The designed architecture reduces the parasitic capacitance and dynamic power by applying full-swing CMOS logic. This architecture redesigns the SAR flip-flops, look-ahead control logic, and digital-to-analog converter switching control network with GDI logic, retaining full-swing CMOS in the comparator, clock distribution, and output restoration paths. The design has been shown to obtain 97 dB SNDR, 15.81-bit ENOB, power consumption of 4.79 mW, a critical path delay of 1226 ps, and a normalized Walden FoM of 185 fJ/ conversion-step, implying its use in low-power, precise applications.
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