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Design issues for high-performance active routers

delete2001-03-01
delete65
PRE
AI
T
Tilman Wolf
T
Turner, JS
DOI：10.1109/49.917702delete
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摘要

摘要

En 中文
Modern networks require the flexibility to support new protocols and network services without changes in the underlying hardware. Routers with general-purpose processors can perform data path packet processing using software that is dynamically distributed. However, custom processing of packets at link speeds requires immense computational power. This paper proposes a design of a scalable, high-performance active router. Multiple network processors with cache and memory on a single application specific integrated circuit are used to overcome the limitations of traditional single processor systems. The proposed design is used as a vehicle for studying the key issues that must be resolved to allow active networking to become a mainstream technology. Benchmark measurements are used to put the design in relation to actual application demands.
Keyword:
active networks
multiprocessor system-on-a-chip
programmable network benchmark
router design
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期刊

IEEE Journal on Selected Areas in Communications 封面图
IEEE Journal on Selected Areas in Communications
IF:
17.2
论文数:
6.4K
被引数:
3.1W

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