.png){kind=icon}
返回
DIA: A Complexity-Effective Decoding Architecture
.png){kind=icon}
OA
AI
DOI：10.1109/TC.2008.170.png)
.png){kind=icon}
.png){kind=icon}
分享.png){kind=icon}
收藏
摘要
En 中文
Fast instruction decoding is a true challenge for the design of CISC microprocessors implementing variable-length instructions. A well-known solution to overcome this problem is caching decoded instructions in a hardware buffer. Fetching already decoded instructions avoids the need for decoding them again, improving processor performance. However, introducing such special-purpose storage in the processor design involves an important increase in the fetch architecture complexity. In this paper, we propose a novel decoding architecture that reduces the fetch engine implementation cost. Instead of using a special-purpose hardware buffer, our proposal stores frequently decoded instructions in the memory hierarchy. The address where the decoded instructions are stored is kept in the branch prediction mechanism, enabling it to guide our decoding architecture. This makes it possible for the processor front end to fetch already decoded instructions from the memory instead of the original nondecoded instructions. Our results show that using our decoding architecture, a state-of-the-art superscalar processor achieves competitive performance improvements, while requiring less chip area and energy consumption in the fetch architecture than a hardware code caching mechanism.
Keyword:
Superscalar processor design
CISC instruction decoding
variable-length ISA
branch predictor
code caching
AI总结
对已上传原文的论文进行重点信息的提取，主要内容包括：简要概述、研究摘要、背景介绍、关键亮点、图文解析、展望与总结。
期刊
IF:
3.8
论文数:
5.3K
被引数:
9.8K
机构
引用论文
分享收藏
Lateral orbitofrontal cortex partitions mechanisms for fear regulation and alcohol consumption.png)
PLOS ONEOAAI
PLOS ONEIF0
OAAI分享收藏分享收藏
查看更多内容