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Direct Neural-Network Hardware-Implementation Algorithm
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DOI：10.1109/TIE.2009.2033097.png)
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摘要
En 中文
An algorithm for compact neural- network hardware implementation is presented, which exploits the special properties of the Boolean functions describing the operation of artificial neurons with step activation function. The algorithm contains three steps: artificial-neural-network (ANN) mathematical model digitization, conversion of the digitized model into a logic-gate structure, and hardware optimization by elimination of redundant logic gates. A set of C++ programs automates algorithm implementation, generating an optimized very high speed integrated circuit hardware description language code. This strategy bridges the gap between ANN design software and hardware design packages (Xilinx). Although the method is directly applicable only to neurons with step activation functions, it can be extended to sigmoidal functions.
Keyword:
Field-programmable gate array (FPGA)
hardware implementation
neural networks
期刊
IF:
7.2
论文数:
1.8W
被引数:
9.8W
机构
引用论文
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