DISCO: Time-Compositional Cache Coherence for Multi-Core Real-Time Embedded Systems

Mohamed Hassan

doi:10.1109/TC.2022.3193624

2023-04-01

PRE

Mohamed Hassan *

DOI：10.1109/TC.2022.3193624

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摘要

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Tasks in modern embedded systems share data and communicate among each other. Nonetheless, the majority of research in real-time systems either assumes that tasks do not share data or prohibits data sharing by design. Only recently, some works investigated solutions to address this limitation and enable data sharing. However, we find these works to suffer from severe limitations. In particular, proposed predictable cache coherence protocols increase the worst-case memory latency (WCL) quadratically due to coherence interference and breaks compositionality by coupling the design and timing analysis of the coherence with the underlying bus arbitration policy. In this paper, we argue that a protocol that distinguishes between non-modifying (read) and modifying (write) memory accesses is key towards reducing the effects of coherence interference on WCL. Accordingly, we propose DISCO, a discriminative coherence solution that capitalizes on this observation to 1) balance average-case performance and WCL, and 2) more importantly, achieves compositionality in the existing of coherence by enabling the decomposition of the effects from coherence and arbitration components. DISCO achieves 7.2x lower latency bounds compared to the state-of-the-art predictable coherence protocol. DISCO also achieves up to 11.4x (5.3x on average) better performance than private cache bypassing for the SPLASH-3 benchmarks.

Keyword:

Coherence

Protocols

Interference

Task analysis

Real-time systems

Hardware

Delays

Cache coherence

real-time systems

timing behavior

time compositionality