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Efficient BinDCT hardware architecture exploration and implementation on FPGA
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DOI：10.1016/j.jare.2016.09.002.png)
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摘要
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This paper presents a hardware module design for the forward Binary Discrete Cosine Transform (BinDCT) and its implementation on a field programmable gate array device. Different architectures of the BinDCT module were explored to ensure the maximum efficiency. The elaboration of these architectures included architectural design, timing and pipeline analysis, hardware description language modeling, design synthesis, and implementation. The developed BinDCT hardware module presents a high efficiency in terms of operating frequency and hardware resources, which has made it suitable for the most recent video standards with high image resolution and refresh frequency. Additionally, the high hardware efficiency of the BinDCT would make it a very good candidate for time and resource-constrained applications. By comparison with several recent implementations of discrete cosine transform approximations, it has been shown that the proposed hardware BinDCT module presents the best performances. (C) 2016 Production and hosting by Elsevier B.V. on behalf of Cairo University.
Keyword:
Binary discrete cosine transform
Discrete cosine transform approximation
Very large scale integration architectures
Hardware implementation
Design exploration
Field programmable gate array
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