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Efficient Majority Voting in Digital Hardware
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AI
DOI：10.1109/TCSII.2022.3144047.png)
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Abstract
En 中文
In recent years, machine learning methods became increasingly important for a manifold number of applications. However, they often suffer from high computational requirements impairing their efficient use in real-time systems, even when employing dedicated hardware accelerators. Ensemble learning methods are especially suitable for hardware acceleration since they can be constructed from individual learners of low complexity and thus offer large parallelization potential. For classification, the outputs of these learners are typically combined by majority voting, which often represents the bottleneck of a hardware accelerator for ensemble inference. In this brief, we present a novel architecture that allows obtaining a majority decision in a number of clock cycles that is logarithmic in the number of inputs. We show, that for the example application of handwritten digit recognition a random forest processing engine employing this majority decision architecture implemented on an FPGA allows the classification of more than seven million images per second, resulting in a speed-up factor of more than 29 compared to the fastest state-of-the-art implementation considered.
Keywords:
Random forests
Clocks
Random access memory
Adders
Field programmable gate arrays
Hardware acceleration
Decoding
Random forests
majority decision
classification
field programmable gate array (FPGA)
hardware acceleration
Journal
I
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4.9
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2.5W