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Efficient Method for Error Detection and Correction in In-Memory Computing Based on Reliable Ex-Logic Gates
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DOI：10.1002/aisy.202200341.png)
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摘要
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In-memory computing using memristor-based stateful logic reveals high efficiency in the computing paradigm where the memory and computation are colocated. Still, variations in the memristor induce reliability issues for practical applications. Previous error detection and correction modules in the inmemory logic gates can handle the errors but only account for nonswitching errors of the output memristor, while the highly probable switching error of the output memristor is neglected, reducing overall efficiency. Moreover, the module operations use other added stateful logic gates, which may add errors. Herein, modules to handle both nonswitching and switching error cases within the three average steps using reliable logic gates consisting of five memristors are proposed. Detecting both error cases allows logic gates to be still operated in the optimized region for high-energy efficiency and stability. In addition, combining two different logic families of stateful and sequential logic gates provides the reliability of the stateful logic gates and a possible solution to the peripheral complexity of cascading sequential logic gates. Although detection and correction are demonstrated in NOR and NAND logic gates with the memristor model, the other logic gates can be applied with the same algorithm with the appropriate module-enable signal and input-checker bits.
Keyword:
error corrections
error detections
in-memory computing
memristors
sequential logic
stateful logic
stateful neural networks
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Memristor crossbar arrays with 6-nm half-pitch and 2-nm critical dimension.png)
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