Efficient multicore-aware parallelization strategies for iterative stencil computations

doi:10.1016/j.jocs.2011.01.010

Efficient multicore-aware parallelization strategies for iterative stencil computations

2011-05-01

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DOI：10.1016/j.jocs.2011.01.010

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Stencil computations consume a major part of runtime in many scientific simulation codes. As prototypes for this class of algorithms we consider the iterative Jacobi and Gauss-Seidel smoothers and aim at highly efficient parallel implementations for cache-based multicore architectures. Temporal cache blocking is a known advanced optimization technique, which can reduce the pressure on the memory bus significantly. We apply and refine this optimization for a recently presented temporal blocking strategy designed to explicitly utilize multicore characteristics. Especially for the case of Gauss-Seidel smoothers we show that simultaneous multi-threading (SMT) can yield substantial performance improvements for our optimized algorithm on some architectures. (C) 2011 Elsevier B.V. All rights reserved.

Keyword:

Stencil computations

Spatial blocking

Temporal blocking

Wavefront parallelization

Multicore

Simultaneous multi-threading

Efficient multicore-aware parallelization strategies for iterative stencil computations

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