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Efficient reference frame compression scheme for video coding systems: algorithm and VLSI design
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DOI：10.1007/s11554-015-0551-1.png)
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摘要
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One of the most concerning issues in current video coding systems relies on the bottleneck caused by the intense external memory access required by motion estimation. As memory access affects directly the energy consumption, this problem becomes more evident when battery-powered devices are considered. In this sense, this article presents the Double Differential Reference Frame Compressor (DDRFC), which is a low-complexity and lossless solution to compress the reference frames before storing them in the external memory. The DDRFC performs intra-block double differential coding over 64 x 64-sample blocks to prepare the data for a static Huffman coding. The DDRFC guarantees block-level random access by avoiding data dependencies between neighboring blocks. It reaches an average compression ratio of 69% for luminance samples for 1080 p video sequences, outperforming any lossless reference frame compressor available in the current literature. Hardware architectures for both the DDRFC encoder and decoder were designed and synthesized targeting FPGA and ASIC 180 and 65-nm standard cells libraries. The synthesis results show that with 65 nm, the DDRFC architectures are able to process 2160 p video at 30 FPS or 1080 p at 120 FPS with a power dissipation of 5.01 mW. The DDRFC codec reaches more than 68% of energy savings when considering memory communication for HD and UHD video processing.
Keyword:
Video coding
HEVC
Lossless reference frame compression
Memory bandwidth reduction
Hardware design
Differential coding
Huffman coding
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