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Efficient Row-Layered Decoder for Sparse Code Multiple Access
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DOI：10.1109/TCSI.2021.3084634.png)
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Abstract
En 中文
Sparse code multiple access (SCMA) is a promising technology for the development of wireless communication, which supports a large number of overloading users and enjoys high spectral efficiency. However, conventional SCMA decoders suffer very high complexity in implementations. Changing the updating scheme is a superior approach to reduce complexity, which guarantees the updated information immediately join in the following message propagating of the current iteration and accelerates the decoding convergence. In this paper, a row-layered message passing algorithm (MPA) is proposed, which offers a good trade-off between the hardware complexity and the bit error rate (BER) performance. Simulation results show that the proposed decoder saves 66.7% computation complexity compared with the original MPA with the similar BER performance. Pipelining and folding technology are adopted in VLSI implementations. The synthesis results with 45-nm CMOS technology show that the proposed decoder can achieve higher hardware efficiency and throughput under a high frequency than the existing decoders, achieving 1777.78 Mb/s throughput with 1.112 mm(2) area consumption.
Keywords:
Decoding
Complexity theory
Hardware
Throughput
Encoding
Jacobian matrices
Iterative decoding
Sparse code multiple access (SCMA)
row-layered message passing algorithm
folding
pipeline
VLSI
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