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Enabling cutting-edge semiconductor simulation through grid technology

delete2009-06-28
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OA
AI
D
Dave Reid *
C
Campbell Millar
S
Scott Roy
G
Gareth Roy
R
Richard Sinnott
G
Gordon Stewart
G
G. A. Stewart
A
Asen Asenov
DOI:10.1098/rsta.2009.0031delete
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摘要

摘要

En 中文
The progressive scaling of complementary metal oxide semiconductor (CMOS) transistors drives the success of the global semiconductor industry. Detailed knowledge of transistor behaviour is necessary to overcome the many fundamental challenges faced by chip and systems designers. Grid technology has enabled the unavoidable statistical variations introduced by scaling to be examined in unprecedented detail. Over 200 000 transistors have been simulated, the results of which provide detailed insight into underlying physical processes. This paper outlines recent scientific results of the nanoCMOS project and describes the way in which the scientific goals have been reflected in the grid-based e-Infrastructure.
Keyword:
nano complementary metal oxide semiconductor electronics
virtual organization
security
variability
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期刊

P
Philosophical Transactions of the Royal Society A-Mathematical Physical and Engineering Sciences
IF:
3.7
论文数:
7.8K
被引数:
2.8W

机构

U
university of glasgow
学者数:
3.5W
论文数: 3.1W
被引数: 37
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