.png){kind=icon}
返回
Energy-aware interconnect optimization for a coarse grained reconfigurable processor
.png){kind=icon}
PRE
AI
DOI：10.1109/VLSI.2008.25.png)
.png){kind=icon}
原文求助.png){kind=icon}
分享.png){kind=icon}
收藏
摘要
En 中文
Modern portable embedded devices provide continuously more features and need processors that are of increasingly higher performance in order to sustain very demanding multimedia and wireless applications. Larger amounts of flexibility need to be built in and the same processor needs to be used for a wide range of evolving products, while very strict energy constraints need to be met in order to provide a long battery life. Coarse Grained Reconfigurable Architectures (CGRAs) provide a mix of flexible computational resources and large amounts of programmable interconnect. However, this programmable interconnect is on average consuming about 50% of the core's energy consumpion for state of the art interconnection topologies. In this work we present an optimized interconnection implementation that selectively activates only the connections that are being used in a certain cycle, in order to reduce the energy spent in the interconnect. Using this optimization, we show the effect on the energy and performance trade-off for the ADRES CGRA. The energy cost of the optimized interconnect topologies that provide a higher performance can be reduced significantly, reducing the total energy consumption of the core with up to 40%. This will enable designers to develop more efficient architectures, tuned to a targeted application domain.
Keyword:
energy-aware design
low power
processor architecture
interconnect-aware design
AI总结
对已上传原文的论文进行重点信息的提取，主要内容包括：简要概述、研究摘要、背景介绍、关键亮点、图文解析、展望与总结。
.png){kind=icon}
