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Enhancing debug observability for HLS-based FPGA circuits through source-to-source compilation
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DOI：10.1016/j.jpdc.2018.02.012.png)
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C-based High Level Synthesis (HLS)-compatible FPGA circuit descriptions from the CHStone benchmark suite are instrumented for debugging purposes using a source-to-source compiler. The debug instrumentation connects C expressions to top-level ports that can be observed during the debugging process. Approximately 50,000 different experiments are conducted to determine the impact on the final circuit caused by the debug instrumentation. Experimental data indicate initial feasibility of the instrumentation approach; all assignment expressions in a program can be instrumented for an average increase in LUT count of about 24%. Increases in FF count and clock period were in the range of 5% to 10%. The source-to-source compiler approach is compatible with many HLS synthesis systems and is flexible and extensible. (C) 2018 Elsevier Inc. All rights reserved.
Keyword:
FPGA
Debug
High level synthesis
Observability
Instrumentation
Productivity
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