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Exploiting Ferroelectric and Spintronic Dynamics for Neural Network Computation
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DOI：10.1002/aisy.70438.png)
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Abstract
En 中文
Analog in-memory computing (AIMC) emerges as a promising solution to overcome the energy and latency bottlenecks in von Neumann architectures for artificial intelligence workloads. Computation is performed directly within arrays of nonvolatile memories. Ferroelectric and spintronic devices, relying on the control of polarization and magnetization, offer intrinsically energy-efficient and low-latency building blocks for AIMC. This review highlights how these two physical hardware families share a unified computational framework: both utilize the hysteretic dynamics of an order parameter to provide nonvolatile, multistate memory and nonlinear switching. To date, most AIMC implementations have been conceived for mature memristive technologies such as RRAM. Because these devices are current-driven, unlike ferroic devices whose operation is field-driven, their associated implementation strategies cannot be directly ported, motivating the need for a new codesign space that this review seeks to establish. We review static, array-based vector–matrix multiplications for machine learning, and dynamical computing paradigms like reservoir computing and spiking neural networks. While device constraints such as quantized value precision, asymmetric weight updates, low-frequency noise, and device nonidealities are often seen as limitations, we show how they can instead be leveraged for training. Learning methods include hardware-aware and physics-aware training, paving the way toward holistic, brain-inspired neuromorphic computing.
Keywords:
analog in-memory computing
ferroelectric
neuromorphic hardware
nonvolatile memory
spintronic
synaptic weight
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