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Exploring FPGA Switch-Blocks without Explicitly Listing Connectivity Patterns
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DOI：10.1145/3597417.png)
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摘要
En 中文
Increased lower metal resistance makes physical aspects of Field-Programmable Gate Array (FPGA) switch-blocks more relevant than before. The need to navigate a design space where each individual switch can have significant impact on the FPGA's performance in turn makes automated switch-pattern exploration techniques increasingly appealing. However, most existing exploration techniques have a fundamental limitation-they use the CAD tools as a black box to evaluate the performance of explicitly listed switch-patterns. Given the time needed to route a modern circuit on a single architecture, the number of switch-patterns that can be explicitly tested quickly becomes negligible compared to the size of the design space. This article presents a technique that removes this fundamental limitation by making the entire design space visible to the router and letting it choose the switches to be added to the pattern, based on the requirements of the circuits being routed. The key to preventing the router from selecting arbitrary switches that would render the final pattern excessively large is to apply the same negotiation principle used by the router to remove congestion, just in the opposite direction, to make the signals reach a consensus on which switches are worthy of being included in the final switch-pattern.
Keyword:
FPGA
interconnect
switch
switch-block
switch-pattern
multiplexer
automated exploration
optimization
design automation
algorithm
avalanche
PathFinder
router
期刊
IF:
2.8
论文数:
599
被引数:
810
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