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Exploring Nanomagnetic Logic with Bennett Clocking

delete2023-08-28
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PRE
AI
P
Pedro Arthur Rodrigues Lopes Silva *
J
Jeferson F. Chaves
J
José Augusto M. Nacif
R
Ricardo Ferreira
O
Omar P. Vilela Neto
DOI:10.1109/SBCCI60457.2023.10261955delete
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摘要

摘要

En 中文
Improving power consumption in integrated circuits can have significant benefits such as increased efficiency, longer battery life for mobile devices, and reduced environmental impact. Promising technologies such as Nanomagnetic Logic (NML), with its inherently low power consumption and principles like reversible computation, offer potential solutions. This paper successfully implements reversible NML circuits using Bennet's clock. Bennett's clock is reversible with theoretically zero power dissipation, allowing us to embed reversibility into NML circuits. To guarantee its functionality, we simulated all the circuits depicted in this paper in a CAD tool. By describing this successful implementation, we hope to pave the way for a more sustainable and energy-efficient future in computing.
Keyword:
nanocomputing
clocking
bennet
reversible computing

期刊

S
SBC and SBMICRO and IEEE and ACM Symposium on Integrated Circuits and Systems Design, SBCCI
IF:
0
论文数:
3
被引数:
0

机构

U
Universidade Federal de Minas Gerais
学者数:
2.5W
论文数: 1.5W
被引数: 1.4W
U
universidade federal de vicosa
学者数:
8.9K
论文数: 5.3K
被引数: 5
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