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FPGA-Based Hardware Implementation of Computationally Efficient Multi-Source DOA Estimation Algorithms
DOI:10.1109/ACCESS.2019.2926335.png)
摘要
En 中文
Hardware implementation of the proposed direction of arrival (DOA) estimation algorithms based on Cholesky and LDL decomposition is presented in this paper. The proposed algorithms are implemented for execution on a field programmable gate array (FPGA) as well as a PC (running LabVIEW) for the multiple non-coherent sources located in the far-field region of a uniform linear array (ULA). Prototype testbeds built using the national instruments (NI) universal software radio peripheral (USRP) software defined radio (SDR) platform and Xilinx Virtex-5 FPGA are originally constructed for the experimental validation of the proposed algorithms. The results from LabVIEW simulations and real-time hardware experiments demonstrate the effectiveness of the proposed algorithms. Specifically, the implementation of the proposed algorithms on a Xilinx Virtex-5 FPGA using the LabVIEW software clarifies their efficiency in terms of computation time and resource utilization, which make them suitable for the real-time practical applications. Moreover, the performance comparison with the QR decomposition-based DOA algorithms as well as similar FPGA-based implementations reported in the literature is conducted in terms of the estimation accuracy, computation speed, and FPGA resources consumed.
Keyword:
Cholesky and LDL decomposition
pipelined architecture
hardware implementation
Xilinx Virtex-5 FPGA
uniform linear array
LabVIEW
direction of arrival estimation
software defined radio
NI USRP-2901
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期刊
IF:
3.6
论文数:
9.8W
被引数:
29.4W
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