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Fully-Parallel Stochastic Decoder for Rate Compatible Modulation
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DOI：10.1109/TCSI.2018.2812779.png)
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Rate compatible modulations (RCMs) are attractive for achieving seamless and blind rate adaptation under time varying channel. Although the decoding of RCM is inherently parallel, the highly complex processing nodes, and routing congestion have prohibited the implementation of fully-parallel decoders for high throughput. In this paper, we propose a new stochastic decoding algorithm for RCM to achieve desired parallel decoding. This algorithm provides even much better decoding performance than the floating-point belief propagation decoding algorithm with 20 iterations. To evaluate the effectiveness of the proposed algorithm, we apply it for the implementation of a field-programmable gate-array fully-parallel stochastic decoder that decodes a 400 x 400 mapping matrix. Several novel structure techniques, including the RAM-based channel stream generator and the configurable variable node, are exploited to reduce the logical resources consumption. The implemented decoder achieves a clock frequency of 220 MHz and provides a maximum throughput about 136Mb/s at SNR = 10 dB and the number of symbols is 400. To the best of our knowledge, this decoder is the first reported fully-parallel RCM decoder which achieves the highest decoding throughput. This research validates the potential of stochastic RCM decoding as a practical approach for area-efficient and high throughput decoders.
Keyword:
Rate compatible modulation (RCM)
iterative decoding
stochastic decoding
field programmable gate array (FPGA)
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