.png){kind=icon}
.png){kind=icon}
Return
Gate insulator stack engineering for fully CMOS-compatible reservoir computing
.png){kind=icon}
OA
AI
DOI：10.1186/s40580-026-00533-5.png)
.png){kind=icon}
.png){kind=icon}
Share.png){kind=icon}
Save
Abstract
En 中文
The need for processing complex and temporal datasets has increased with the rise of artificial intelligence. In this context, reservoir computing, which utilizes the short-term memory of the reservoir to map input data into a high-dimensional space, has gathered significant interest. In this study, for the first time, fully CMOS-compatible reservoir computing is demonstrated through gate insulator stack engineering. Integrated on a single wafer, CMOS circuits, Al2O3/Si3N4 (A/N) devices for both reservoir and leaky integrate-and-fire neuron applications, and Al2O3/Si3N4/SiO2 (A/N/O) devices as synaptic devices are verified. Furthermore, the influence of various bias conditions on reservoir performance is analyzed. The proposed co-integrated reservoir computing system efficiently handles temporal data, reducing ~ 53% of network resources with only ~ 0.17%p accuracy drop while being robust to device variations.
Keywords:
Reservoir computing
Neuromorphic computing
Spiking neural networks
Charge-trap
Flash memory
Integration
AI Summary
Key information extracted from the uploaded paper, including a brief overview, abstract, background, key highlights, visual analysis, and future outlook.
Journal
N
IF:
11
Papers:
545
Citations:
3.8K
Organization
View more organizations