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Generating Efficient Instruction Sequence for Software-Based Self-Testing of Processor Cores Using Reinforcement Learning
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DOI：10.1109/ACCESS.2024.3516389.png)
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As the prevalence of faulty chips increases post-deployment, effective in-field testing is imperative. This paper introduces a novel approach for generating software-based self-test (SBST) programs for processor cores using reinforcement learning (RL). We employ toggle coverage as a proxy metric to streamline the RL training process, reducing the significant overhead typically associated with evaluating coverage metrics for reward determination. The efficacy of our method is demonstrated through testing on two types of RISC-V cores, where it markedly outperforms traditional random-based generation methods. Notably, our approach achieves over 80% toggle coverage with merely 200 instructions. Further assessments using the stuck-at-fault model show a substantial improvement in fault coverage, exceeding that of random methods by 1.7 times in out-of-order cores and attaining more than 90% stuck-at-fault coverage within the same instruction count. These findings highlight the efficiency and potential of our method for robust in-field processor testing.
Keyword:
Circuit faults
Logic gates
Training
Out of order
Measurement
Reinforcement learning
Registers
Probability distribution
Manufacturing
Manuals
Software-based self-testing (SBST)
reinforcement learning (RL)
期刊
IF:
3.6
论文数:
9.8W
被引数:
29.4W
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