GPU Implementation of Bitplane Coding with Parallel Coefficient Processing for High Performance Image Compression

Pablo Enfedaque

doi:10.1109/TPDS.2017.2657506

2017-08-01

Pablo Enfedaque *

Francesc Aulí-Llinàs

Juan Carlos Moure

DOI：10.1109/TPDS.2017.2657506

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摘要

En 中文

The fast compression of images is a requisite in many applications like TV production, teleconferencing, or digital cinema. Many of the algorithms employed in current image compression standards are inherently sequential. High performance implementations of such algorithms often require specialized hardware like field integrated gate arrays. Graphics Processing Units (GPUs) do not commonly achieve high performance on these algorithms because they do not exhibit fine-grain parallelism. Our previous work introduced a new core algorithm for wavelet-based image coding systems. It is tailored for massive parallel architectures. It is called bitplane coding with parallel coefficient processing (BPC-PaCo). This paper introduces the first high performance, GPU-based implementation of BPC-PaCo. A detailed analysis of the algorithm aids its implementation in the GPU. The main insights behind the proposed codec are an efficient thread-to-data mapping, a smart memory management, and the use of efficient cooperation mechanisms to enable inter-thread communication. Experimental results indicate that the proposed implementation matches the requirements for high resolution (4 K) digital cinema in real time, yielding speedups of 30x with respect to the fastest implementations of current compression standards. Also, a power consumption evaluation shows that our implementation consumes 40x less energy for equivalent performance than state-of-the-art methods.

Keyword:

Image coding

SIMD computing

graphics processing unit (GPU)

compute unified device architecture (CUDA)