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Graph-based evolutionary design of arithmetic circuits
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DOI：10.1109/4235.985694.png)
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In this paper, we present an efficient graph-based evolutionary optimization technique called evolutionary graph generation (EGG) and the proposed approach is applied to the design of combinational and sequential arithmetic circuits based on parallel counter-tree architecture. The fundamental idea of EGG is to employ general circuit graphs as individuals and manipulate the circuit graphs directly using new evolutionary graph operations without encoding the graphs into other indirect representations, such as bit strings used in genetic algorithm (GA) proposed by Holland and trees used in genetic programming (GP) proposed by Koza et al. In this paper, the EGG system is applied to the design of constant-coefficient multipliers and the design of bit-serial data-parallel adders. The results demonstrate the potential capability of EGG to solve the practical design problems for arithmetic circuits with limited knowledge of computer arithmetic algorithms. For example, in the design of fast constant-coefficient multipliers consisting of shifters and parallel counters, the results obtained from the EGG are superior to or as good as the known conventional designs using arithmetic algorithms. This means that the proposed EGG system can help to simplify and speed up the process of designing arithmetic circuits and can produce better solutions to the given problem.
Keyword:
arithmetic circuits
canonic signed-digit (CSD) representation
digital signal processing (DSP)
electronic design automation (EDA)
evolutionary computation
evolutionary graph generation (EGG)
multipliers
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12
论文数:
1.9K
被引数:
2.4W
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