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Greedy algorithm based circuit optimization for near-term quantum simulation
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DOI：10.1088/2058-9565/ac796b.png)
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Simulating quantum systems is believed to be one of the most important applications of quantum computers. On noisy intermediate-scale quantum (NISQ) devices, the high-level circuit designed by quantum algorithms for Hamiltonian simulation needs to consider hardware limitations such as gate errors and circuit depth before it can be efficiently executed. In this work, we develop a hardware-agnostic circuit optimization algorithm to reduce the overall circuit cost for Hamiltonian simulation problems. Our method employ a novel sub-circuit synthesis in intermediate representation and propose a greedy ordering scheme for gate cancellation to minimize the gate count and circuit depth. To quantify the benefits of this approach, we benchmark proposed algorithm on different Hamiltonian models. Compared with state-of-the-art generic quantum compilers and specific quantum simulation compiler, the benchmarking results of our algorithm show an average reduction in circuit depth by 16.5x (up to 64.1x) and in gate count by 7.8x (up to 23.7x). This significant improvement helps enhance the performance of Hamiltonian simulation in the NISQ era.
Keyword:
noisy intermediate-scale quantum (NISQ) algorithm
Hamiltonian simulation
circuit optimization
circuit depth reduction
greedy algorithm
gate cancellation
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