Hardware Acceleration for Machine Learning

doi:10.3390/electronics15091857

2026-04-28

Sergio Spanò *

Gian Carlo Cardarilli

Luca Di Nunzio

DOI：10.3390/electronics15091857

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Keyword:

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期刊

Electronics

IF:

2.6

论文数:

1.1W

被引数:

4.7W

机构

Tor Vergata University of Rome

学者数:

245

论文数: 101

被引数: 0

引用论文

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Zhang, J.; Yu, J.; Qiu, N.; Liu, Y.; Song, Y.; Zhang, L.; Du, S. Advanced artificial intelligence algorithms and hardware acceleration techniques applied to material structure design. AI Mater. 2026, 2, 3. [Google Scholar] [CrossRef]张, J.; 俞, J.; 邱, N.; 刘, Y.; 宋, Y.; 张, L.; 杜, S. 先进的人工智能算法和硬件加速技术应用于材料结构设计. AI Mater. 2026, 2, 3. [Google Scholar] [CrossRef]

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2025-06-21

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Xu, B.; Banerjee, A.; Gupta, S. Hardware Acceleration for Neural Networks: A Comprehensive Survey. arXiv 2025, arXiv:2512.23914. [Google Scholar] [CrossRef]徐等人；巴纳吉；古普塔。神经网络硬件加速：全面综述。arXiv 2025，arXiv:2512.23914。 [谷歌学术] [CrossRef]

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