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Hardware Architecture Proposal for TEDA Algorithm to Data Streaming Anomaly Detection
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DOI：10.1109/ACCESS.2021.3098004.png)
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摘要
En 中文
The amount of data in real-time, such as time series and streaming data, available today continues to grow. Being able to analyze this data the moment it arrives can bring an immense added value. However, it also requires a lot of computational effort and new acceleration techniques. As a possible solution to this problem, this paper proposes a hardware architecture for Typicality and Eccentricity Data Analytic (TEDA) algorithm implemented on Field Programmable Gate Arrays (FPGA) for use in data streaming anomaly detection. TEDA is based on a new approach to outlier detection in the data stream context. The suggested design has a full parallel input of N elements and a 3-stage pipelined architecture to reduce the critical path and thus optimize the throughput. In order to validate the proposals, results of the occupation and throughput of the proposed hardware are presented. The design reached a speed of up to 693x, compared to other software platforms, with a throughput of up to 10.96 MSPs (Mega Sample Per second), using a small portion of the target FPGA resources. Besides, the bit accurate simulation results are also presented. This work is a pioneer in the hardware implementation of the TEDA technique in FPGA. The project aims to Xilinx Virtex-6 xc6vlx240t-1ff1156 as the target FPGA.
Keyword:
Field programmable gate arrays
Anomaly detection
Hardware
Real-time systems
Throughput
Computer architecture
Proposals
Data streaming
FPGA
anomaly detection
TEDA
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期刊
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3.6
论文数:
9.8W
被引数:
29.4W
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