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Hardware-Efficient and High-Throughput LLRC Segregation Based Binary QC-LDPC Decoding Algorithm and Architecture
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DOI：10.1109/TCSII.2021.3071804.png)
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This brief proposes hardware-friendly QC-LDPC decoding algorithm with layered scheduling based on new logarithmic-likelihood-ratio compound (LLRC) segregation technique. Subsequently, we present hardware-efficient QC-LDPC decoder-architecture based on the proposed algorithm and additional architectural optimizations. This decoder has been designed based on the 5G-NR specifications, supporting code-lengths and code-rates in the ranges of 26112-10368 bits and 1/3-8/9, respectively. Performance analysis has shown that suggested LLRC-segregation based decoding algorithm delivers adequate FER of 10(-5) between 1 to 6.5 dB of SNR range. Furthermore, proposed QC-LDPC decoder is post-route simulated and implemented on the FPGA platform. It operates at a maximum clock frequency of 135 MHz and delivers a peak throughput of 11.02 Gbps. Eventually, comparison with relevant works shows that our decoder delivers 2.2x higher throughput and 8.3x better hardware-efficiency than the state-of-the-art implementations.
Keyword:
Wireless communication
quasi-cyclic low-density-parity-check (QC-LDPC) codes
field-programmable gate-array (FPGA)
frame error rate (FER)
signal-to-noise ratio (SNR)
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