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Hardware for Deep Learning Acceleration

delete2024-03-21
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C
Choongseok Song
C
ChangMin Ye
Y
Yonguk Sim
D
Doo Seok Jeong *
DOI:10.1002/aisy.202300762delete
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摘要

摘要

En 中文
Deep learning (DL) has proven to be one of the most pivotal components of machine learning given its notable performance in a variety of application domains. Neural networks (NNs) for DL are tailored to specific application domains by varying in their topology and activation nodes. Nevertheless, the major operation type (with the largest computational complexity) is commonly multiply-accumulate operation irrespective of their topology. Recent trends in DL highlight the evolution of NNs such that they become deeper and larger, and thus their prohibitive computational complexity. To cope with the consequent prohibitive latency for computation, 1) general-purpose hardware, e.g., central processing units and graphics processing units, has been redesigned, and 2) various DL accelerators have been newly introduced, e.g., neural processing units, and computing-in-memory units for deep NN-based DL, and neuromorphic processors for spiking NN-based DL. In this review, these accelerators and their pros and cons are overviewed with particular focus on their performance and memory bandwidth. In this review, various platforms for deep learning accelerations, such as central processing units, graphics processing units, neural processing units, compute-in-memory units, and neuromorphic event processors, are overviewed and they are compared with regard to the key performance metrics, such as operational throughput, power efficiency, versatility, and flexibility.image (c) 2024 WILEY-VCH GmbH
Keyword:
compute-in-memory
deep learning
deep learning accelerators
graphics processing units
neural processing units
neuromorphic processors
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Advanced Intelligent Systems 封面图
Advanced Intelligent Systems
IF:
6.1
论文数:
2.0K
被引数:
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hanyang university
学者数:
2.9W
论文数: 2.7W
被引数: 36
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