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Hardware implementation of Bayesian network based on two-dimensional memtransistors
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DOI：10.1038/s41467-022-33053-x.png)
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摘要
En 中文
Bayesian networks (BNs) find widespread application in many real-world probabilistic problems including diagnostics, forecasting, computer vision, etc. The basic computing primitive for BNs is a stochastic bit (s-bit) generator that can control the probability of obtaining '1' in a binary bit-stream. While silicon-based complementary metal-oxide-semiconductor (CMOS) technology can be used for hardware implementation of BNs, the lack of inherent stochasticity makes it area and energy inefficient. On the other hand, memristors and spintronic devices offer inherent stochasticity but lack computing ability beyond simple vector matrix multiplication due to their two-terminal nature and rely on extensive CMOS peripherals for BN implementation, which limits area and energy efficiency. Here, we circumvent these challenges by introducing a hardware platform based on 2D memtransistors. First, we experimentally demonstrate a low-power and compact s-bit generator circuit that exploits cycle-to-cycle fluctuation in the post-programmed conductance state of 2D memtransistors. Next, the s-bit generators are monolithically integrated with 2D memtransistor-based logic gates to implement BNs. Our findings highlight the potential for 2D memtransistor-based integrated circuits for non-von Neumann computing applications. Bayesian networks are applied to resolve several types of probabilistic problems. Here, Das et al. develop a stochastic computing hardware platform using two-dimensional memtransistors for the implementation of Bayesian network with high accuracy.
Keyword:
NUMBER GENERATOR
TELEGRAPH NOISE
MOS2
TRANSISTORS
BENCHMARKING
PROSPECTS
DEVICES
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15.7
论文数:
9.4W
被引数:
91.2W
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