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Hardware Patching Methodology for Neutralizing Timing Hardware Trojans Using Vulnerability Analysis and Time Borrowing Scheme
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DOI：10.1109/TCSII.2022.3160489.png)
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摘要
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Outsourcing of the design and IC fabrication to the untrusted entities increases the risk of hardware Trojan insertion in different stages of IC's life cycle. In this brief, we propose a pre-silicon modification scheme, aiming at detecting and compensating the adverse effect of timing hardware Trojans (THT) using a time borrowing approach. The key idea is that a circuit path under tamper in which the setup time is violated can borrow some time from the following stage if it has enough positive timing slack to donate. Accordingly, we modify the original circuit by employing the Dynamic flip-flop Conversion (DFFC) structures to convert the suspected flip-flops into a single transparent latch. A new timing vulnerability analysis including the path-delay and structural analysis along with the proposed test pattern generation scheme is also developed to exploit the vulnerable paths suitable for DFFC insertion. The experimental results show that the insertion of DFFC structures can effectively predict timing errors higher than 1.4% of the critical path-delay while it can fully restore the Trojan-infected paths back to its normal state by compensating 100% of the injected delays ranging from 39% to 81% of the critical path.
Keyword:
Trojan horses
Hardware
Flip-flops
Delays
Latches
Clocks
Capacitance
Hardware security
timing hardware Trojan
path-delay analysis
logic testing
DFFC
期刊
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4.9
论文数:
8.8K
被引数:
2.5W
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