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High-performance DRAMs in workstation environments
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DOI：10.1109/12.966491.png)
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摘要
En 中文
This paper presents a simulation-based performance study of several of the new high-performance DRAM architectures, each evaluated In a small system organization. These small-system organizations correspond to workstation-class computers and use only a handful of DRAM chips (similar to 10, as opposed to similar to1 or similar to 100). The study covers Fast Page Mode, Extended Data Out, Synchronous, Enhanced Synchronous, Double Data Rate, Synchronous Link, Rambus, and Direct Rambus designs. Our simulations reveal several things: 1) Current advanced DRAM technologies are attacking the memory bandwidth problem but not the latency problem; 2) bus transmission speed will soon become a primary factor limiting memory-system performance; 3) the post-L2 address stream still contains significant locality, though it varies from application to application; 4) systems without L2 caches are feasible for low- and medium-speed CPUs (1 GHz and below); and 5) as we move to wider buses, row access time becomes more prominent, making it important to investigate techniques to exploit the available locality to decrease access time.
Keyword:
DRAM architectures
DRAM performance
DRAM systems
system modeling
DDR DRAM
Direct Rambus DRAM
PC100SDRAM
DDR2 DRAM