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High Performance Hardware Architectures for One Bit Transform Based Single and Multiple Reference Frame Motion Estimation
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DOI：10.1109/TCE.2010.5506051.png)
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摘要
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Motion Estimation (ME) is the most computationally intensive part of video compression and video enhancement systems. One bit transform (1BT) based ME algorithms have low computational complexity. Therefore, in this paper, we propose high performance systolic hardware architectures for 1BT based fixed block size (FBS) single reference frame (SRF) ME, variable block size (VBS) SRF ME, and multiple reference frame (MRF) ME. The proposed FBS-SRF ME hardware performs full search ME for 4 Macroblocks in parallel and it is faster than the 1BT based ME hardware reported in the literature. In addition, it uses less on-chip memory than the previous 1BT based ME hardware by using a novel data reuse scheme and memory organization. The proposed VBS-SRF ME hardware is also faster and uses less on-chip memory than previous 1BT based VBS-SRF ME hardware. The proposed MRF ME hardware is the first 1BT based MRF ME hardware in the literature. In order to trade-off ME performance and computational complexity, the proposed MRF ME hardware is designed as reconfigurable in order to statically configure the number and selection of reference frames based on the application requirements. The proposed hardware architectures are implemented in Verilog HDL. They are capable of processing 83 1920x1080 full High Definition frames per second. Therefore, they can be used in consumer electronics products that require real-time video processing or compression.(1)
Keyword:
Motion Estimation
Multiple Reference Frame
One Bit Transform
Hardware Implementation
FPGA
期刊
IF:
10.9
论文数:
5.3K
被引数:
6.8K
机构
引用论文
An All Binary Sub-Pixel Motion Estimation Approach and its Hardware Architecture一种全二值亚像素运动估计方法及其硬件结构
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