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High-Resolution ADC Linearity Testing Using a Fully Digital-Compatible BIST Strategy
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DOI：10.1109/TIM.2009.2015703.png)
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摘要
En 中文
This paper proposes a digital-compatible built-in self-test (BIST) strategy for high-resolution analog-to-digital converter (ADC) linearity testing using only digital testing environments. The on-chip stimulus generator consists of three low-resolution and low-accuracy current steering digital-to-analog converters (DACs), which are area efficient and easy to design. The linearity of the stimuli is improved by the proposed reconfiguration technique. ADCs' outputs are evaluated by simple digital logic circuits to characterize the nonlinearities. The proposed BIST strategy is capable of characterizing ADC transition levels one by one with small hardware overhead. The testing performance is not sensitive to the mismatches and process variations, so that the analog BIST circuits can easily be reused without complex self-calibration. Simulation and experimental results show that the proposed circuitry and BIST strategy can test the INLk error of 12-bit ADCs to a +/- 0.15 least significant bit (LSB) accuracy level using only 7-bit linear DACs.
Keyword:
Analog-to-digital converters (ADCs)
built-in self-test (BIST)
deterministic dynamic element matching (DDEM)
embedded test
integral nonlinearity (INL)
static linearity testing
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期刊
IF:
5.9
论文数:
2.0W
被引数:
5.8W
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分享收藏分享收藏Testing high-resolution ADCs with low-resolution/accuracy deterministic dynamic element matched DACs
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分享收藏A deterministic dynamic element matching approach for testing high-resolution ADCs with low-accuracy excitations用于测试具有低精度激励的高分辨率adc的确定性动态元素匹配方法
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