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High Resolution Digital Imager Based on Time Multiplexing Algorithm
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DOI：10.1109/JSEN.2017.2682226.png)
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摘要
En 中文
In this paper, a new high-resolution digital imager based on a time multiplexing scheme is proposed. The imager produces a 256-grayscale image through capturing 256 successive frames that each belongs to a specific luminance range. Each pixel includes a 1-b analog-to-digital converter (ADC) and a single bit static memory to improve the fill factor. The in-pixel ADC is designed as a compact and fast converter to achieve a high-resolution and video-rate image sensor. The proposed sensor is designed and implemented in a standard 180-nm CMOS technology. The imager achieves an overall dynamic range of over 140 dB at video rate imaging. The pixel pitch is 18.3 mu m and the fill factor is about 48%. The circuit operates at a supply voltage as low as 800 mV. At this supply voltage and at video rate imaging, its power consumption is about 4.33 nW. The proposed imager can directly perform some pre-processing algorithms, such as image segmentation and binarization. Additionally, the proposed method transfers the memory and process units of the pixels to the external of the sensor array so it provides a suitable structure for designing high-resolution, wide dynamic range, and fast general-purpose image sensors.
Keyword:
CMOS image sensor
digital pixel sensor (DPS)
high-resolution image sensor
low-power
pulse-width modulation (PWM)
smart vision chip
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4.5
论文数:
2.2W
被引数:
7.3W
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