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High-speed and area-efficient arithmetic and logic unit architecture using quantum-dot cellular automata for digital signal processing
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DOI：10.1016/j.nancom.2025.100574.png)
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Abstract
En 中文
Signal processing has significantly influenced our lives in many domains, including telecommunications, education, healthcare, industry, and security. The efficiency of signal processing heavily relies on the Arithmetic and Logic Unit (ALU), which stands as an essential hardware component. In addition, ALU is a fundamental part of a central processing unit (CPU), leading to fundamental operations inside the processor. However, the growing demand for small, robust hardware systems has led researchers to create nano-electronic technologies under consideration. One of the leading technologies in this field is Quantum-dot cellular automata (QCA), which demonstrates promising value as a possible alternative to complementary metal-oxide-semiconductor (CMOS) designs since it enables compact circuit designs with minimal power consumption. The existing QCA-based ALU designs face limitations in cell count density together with high occupied area and high delay, which reduces their performance for real-time signal processing. This research presents a 1-bit ALU through a QCA-optimized approach for DSP applications. QCADesigner is used to validate and verify all proposed designs. Results show a statistically significant improvement in cell count reduction of 46.84 % and a total occupied area of 64.28 % lower than the most advanced version published to date.
Keywords:
Arithmetic and logic unit (ALU)
Quantum dot cellular automata (QCA)
Microcontroller
Signal processing
Nanotechnology