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High-speed FPGA-based phase measuring profilometry architecture
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DOI：10.1364/OE.25.010553.png)
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Abstract
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This paper proposes a high-speed FPGA architecture for the phase measuring profilometry (PMP) algorithm. The whole PMP algorithm is designed and implemented based on the principle of full-pipeline and parallelism. The results show that the accuracy of the FPGA system is comparable with those of current top-performing software implementations. The FPGA system achieves 3D sharp reconstruction using 12 phase-shifting images and completes in 21 ms with 1024 x 768 pixel resolution. To the best of our knowledge, this is the first fully pipelined architecture for PMP systems, and this makes the PMP system very suitable for high-speed embedded 3D shape measurement applications. (C) 2017 Optical Society of America
Keywords:
3-D SHAPE MEASUREMENT
REAL-TIME
UNWRAPPING ALGORITHMS
DESIGN
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