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High-speed parallel-prefix module 2n-1 adders
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DOI：10.1109/12.863036.png)
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A novel parallel-prefix architecture for high speed module 2(n) - 1 adders is presented. The proposed architecture is based on the idea of recirculating the generate and propagate signals, instead of the traditional end-around carry approach. Static CMOS implementations verify that the proposed architecture compares favorably with the already known parallel-prefix or carry look-ahead structures.
Keyword:
modulo 2(n)-1 adders
parallel-prefix adders
carry look-ahead adders
VLSI design
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3.8
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5.4K
被引数:
9.8K
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