.png){kind=icon}
返回
High-Throughput Layered Decoder Implementation for Quasi-Cyclic LDPC Codes
.png){kind=icon}
PRE
AI
DOI：10.1109/JSAC.2009.090816.png)
.png){kind=icon}
原文求助.png){kind=icon}
分享.png){kind=icon}
收藏
摘要
En 中文
This paper presents a high-throughput decoder design for the Quasi-Cyclic (QC) Low-Density Parity-Check (LDPC) codes. Two new techniques are proposed, including parallel layered decoding architecture (PLDA) and critical path splitting. PLDA enables parallel processing for all layers by establishing dedicated message passing paths among them. The decoder avoids crossbar-based large interconnect network. Critical path splitting technique is based on articulate adjustment of the starting point of each layer to maximize the time intervals between adjacent layers, such that the critical path delay can be split into pipeline stages. Furthermore, min-sum and loosely coupled algorithms are employed for area efficiency. As a case study, a rate-1/2 2304-bit irregular LDPC decoder is implemented using ASIC design in 90nm CMOS process. The decoder can achieve the maximum decoding throughput of 2.2Gbps at 10 iterations. The operating frequency is 950MHz after synthesis and the chip area is 2.9mm(2).
Keyword:
Low-density parity-check codes
quasi-cyclic codes
parallel architecture
layered decoding
critical path splitting
min-sum algorithm
loosely coupled algorithm
VLSI
AI总结
对已上传原文的论文进行重点信息的提取，主要内容包括：简要概述、研究摘要、背景介绍、关键亮点、图文解析、展望与总结。
期刊
IF:
17.2
论文数:
6.4K
被引数:
3.1W
机构
引用论文
.png){kind=icon}
分享收藏
Reduced complexity iterative decoding of low-density parity check codes based on belief propagation基于置信传播的低密度奇偶校验码迭代译码复杂度降低
PREAI
分享收藏分享收藏
查看更多内容