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Highly Parallel Multi-FPGA System Compilation from Sequential C/C plus plus Code in the AWS Cloud
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DOI：10.1145/3507698.png)
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摘要
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We present a High Level Synthesis compiler that automatically obtains a multi-chip accelerator system from a single-threaded sequential C/C++ application. Invoking the multi-chip accelerator is functionally identical to invoking the single-threaded sequential code the multi-chip accelerator is compiled from. Therefore, software development for using the multi-chip accelerator hardware is simplified, but the multi-chip accelerator can exhibit extremely high parallelism. We have implemented, tested, and verified our push-button system design model on multiple field-programmable gate arrays (FPGAs) of the Amazon Web Services EC2 F1 instances platform, using, as an example, a sequential-natured DES key search application that does not have any WALL loops and that tries each candidate key in order and stops as soon as a correct key is found. An 8-FPGA accelerator produced by our compiler achieves 44.600 times better performance than an x86 Xeon CPU executing the sequential single-threaded C program the accelerator was compiled from. New features of our compiler system include: an ability to parallelize outer loops with loop-carried control dependences, an ability to pipeline an outer loop without fully unrolling its inner loops, and fully automated deployment, execution and termination of multi-FPGA application-specific accelerators in the AWS cloud, without requiring any manual steps.
Keyword:
Multi-FPGA
hierarchical software pipelining
high-level synthesis
compilers
AWS cloud
DES cracker
期刊
IF:
2.8
论文数:
598
被引数:
810
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