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i-SRAM: Interleaved Wordlines for Vector Boolean Operations Using SRAMs
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DOI：10.1109/TCSI.2020.3005783.png)
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Abstract
En 中文
The generic approach toward SRAM based in- memory computations has been to activate multiple memory rows simultaneously and read out a logic function of the constituent rows. In general, these schemes introduce errors in computations due to their analog nature, limiting their usage to error-resilient applications such as machine learning. In contrast, in-memory bulk bit-wise Boolean computations are suitable not only for error-resilient applications, but also those that require accurate computations like encryption. Prior works have indeed accomplished such bit-wise computations, however, they require modifications to the normal SRAM read operations leading to degraded read-stability or lower sense-margin. In this paper, we propose interleaving the word-lines (i-SRAM) as the basic approach for embedding bit-wise computations in SRAM arrays. Further, our i-SRAM read operation is identical to the normal memory read operation without loss of read-robustness or sensemargin. Even at deeply scaled nodes, as long as normal SRAM read stability is ascertained, the presented proposal works equally well. As opposed to prior works, this is a key benefactor in allowing the proposal to be seamlessly integrated in state-of-the-art SRAM compilers. We propose different configurations of i-SRAM for 6T and 8T-bit-cells, with minimal area overhead. We further demonstrate upto similar to 2x improvement in energy and similar to 8x improvement in throughput for a binary neural network (BNN) and similar to 3.5x improvement in energy and similar to 3x improvement in throughput for AES encryption using the proposed i-SRAM in a modified von-Neuamnn machine.
Keywords:
Random access memory
Logic gates
Arrays
Standards
Proposals
Layout
Throughput
In-memory computing
interleaved word-lines
SRAMs
von Neumann bottleneck
binary neural network
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