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Identification of design errors through functional testing
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DOI：10.1109/TR.2003.821926.png)
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摘要
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Verification of the functionality of VHDL specifications is one of the primary and most time consuming tasks of design. However, it must necessarily be an incomplete task because it is impossible to completely exercise the specification by exhaustively applying all input patterns. We present a two-step strategy based on symbolic analysis of the VHDL specification, using a behavioral error model. First, we generate a reduced number of functional test vectors for each process of the specification by using a new analysis metric which we call bit coverage. The error model based on this metric allows the identification of possible design errors represented by redundancies in the VHDL code. Then, through the definition of a controllability measure, we verify if these functional test vectors can be applied to the process inputs when it is interconnected to other processes. If this is not the case, the analysis of the nonapplicable inputs provides identification of possible design errors due to erroneous interconnections. The bit-coverage provides complete statement, condition and branch coverage; and we experimentally show that it allows the identification of possible design errors. Identification and removal of design errors improves the global testability of a design.
Keyword:
ATPG
implementation verification
symbolic techniques
test synthesis
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