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Improved Method for Paralleling Reduced Switch VSI Modules: Harmonic Content and Circulating Current
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DOI：10.1109/TPEL.2013.2280723.png)
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摘要
En 中文
A new zero-sequence circulating current (ZSCC) reduction method for multimodule voltage source inverters (MVSIs) consisting of P three-phase inverters that are connected in parallel is proposed in this paper. Four-switch inverter modules are used instead of the conventional six-switch modules to reduce the cost. In this paper, the effectiveness of the proposed ZSCC reduction method is studied using selective harmonic elimination pulse width modulation. The proposed ZSCC reduction method can remove about P times the number of harmonics using the same switching frequency as compared to more conventional methods, as explained later in this paper. The concepts discussed in the paper are confirmed with results obtained from an MVSI experimental prototype.
Keyword:
Parallel converters
pulse width modulation (PWM)
selective harmonic elimination (SHE)
voltage source inverter (VSI)
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6.5
论文数:
1.7W
被引数:
8.3W
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