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Improving energy efficiency using a link adaptation algorithm dedicated for 100 Gbps wireless communication
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DOI：10.1016/j.aeue.2017.07.005.png)
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This paper presents a link adaptation algorithm dedicated for 100 Gbps wireless transmission. Interleaved Reed-Solomon codes are selected as forward error correction (FEC) algorithms. The redundancy of the codes is selected according to the channel bit error rate (BER). The uncomplicated FEC scheme allows implementing a complete data link layer processor in an FPGA (field programmable gate array). In our case, we use the Virtex7 FPGA to validate the functionality of our implementation. The proposed FPGA-processor achieves 169 Gbps throughput. Moreover, the implementation is synthesized into 40 nm CMOS technology and the described link adaptation algorithm allows reducing consumed energy per bit to values below 1 pJ/bit at BER
Keyword:
Link adaptation
100 Gbps wireless
Energy consumption
40 nm ASIC
Data link layer processing
Interleaved Reed-Solomon
FPGA
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